1. Field of Invention
This invention relates to a semiconductor assembly package. More particularly, the present invention is related to a multi-chips bumpless assembly package and a manufacturing method thereof.
2. Related Art
Integrated circuits (chip) packaging technology is becoming a limiting factor for the development in packaged integrated circuits of higher performance. Semiconductor package designers are struggling to keep pace with the increase in pin count, size limitations, low profile, and other evolving requirements for packaging and mounting integrated circuits.
Originally, the electrical connections between the chips comprise wire bonding connection and flip chip connection. In wire bonding connection, a wire bonder is disposed above the first chip and then the tip of the conductive wire is melting to shape into a ball. Next, the conductive wire is bonded onto the bonding pad of the first chip. Then, the wire bonder is moved and disposed above the corresponding bonding pad of the second chip, and then the conductive wire will be bonded onto the corresponding bonding pad of the second chip to complete wire bonding the first chip and the second chip. In flip chip bonding, a plurality of bumps are formed on the bonding pads of the chip, and then flipped and bonded to another chip by a reflow process.
However, as shown above, in the wire-bonding package, when the chips are stacked with each other to form a stacked package, the wires connecting the upper chip and the substrate are longer. In such a manner, said wires are easily to be damaged due to the molding flow attacking the wires. In addition, when the flip chip are stacked with each to form a stacked package, there are usually needed to form a redistributed layers on the back side of the chips and utilizing another wires for electrically connecting the chips to the substrate. Thus, the process will become more complex. Besides, as shown in FIG. 1A, it illustrates a multi-chips stacked package patented in U.S. Pat. No. 5,399,898 to Michael D. Rostoker et al. entitled “Multi-Chip Semiconductor Arrangements Using Flip Chip Dies” and each of said chips 30 has bumps 20A and 20B formed on the double sides; and the bumps 20B on the upper side are utilized to connect to an external devices, such as the same chip 30 as shown in FIG. 1B, placed over the chip 30 and the bumps 20A on the lower side are utilized to connect to an external device, such as the contact 10 of the substrate as shown in FIG. 1B, disposed under the chip 30. To be noted, the bumps 20A and 20B are electrically connected to each other through the electrical traces formed inside the chip 30. However, the manufacturing method of such chip is more complex than conventional one. Besides, it is more difficult to control the collapse of the bumps 20A and 20B, when such chip is interposed between electronic devices, due to the bumps 20A and 20B formed on the double sides.
Therefore, providing another semiconductor assembly package to solve the mentioned-above disadvantages is the most important task in this invention.